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this document is a general product descript ion and is subject to change without notice. hynix does not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.0 / jul. 2008 1 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 8 gb nand flash H27U8G8T2B www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 2 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash document title 8 gbit (1024 m x 8 bi t) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. jul. 30. 2008 preliminary www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 3 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications multiplane architecture - array is split into two independent planes. parallel opera- tions on both planes are ava ilable, halving program, read and erase time. nand interface - x8 bus width. - address / data multiplexing - pin-out compatibility for all densities supply voltage - 3.3 v device : vcc = 2.7 v ~3.6 v memory cell array - (4 k + 128) bytes x 128 pages x 2048 blocks page size - (4 k + 128 spare) bytes block size - (512 k + 16 k spare) bytes page read / program - random access : 60 us (max.) - sequential access : 25 ns (min.) - page program time : 800 us (typ.) - multi-plane program time (2 pages) : 800 us (typ.) fast block erase - block erase time: 2.5 ms (typ.) - multi-block erase time (2 blocks) : 2.5 ms (typ.) electronic signature - 1st cycle : manufacturer code - 2nd cycle : device code - 3rd cycle : internal chip numb er, cell type, number of si- multaneously programmed pages. - 4th cycle : page size, block size, organization, spare size - 5th cycle : multiplane information copy back program - fast data copy without external buffer chip enable don't care - simple interface with microcontroller status register - normal status register (read/program/erase) hardware data protection - device locked during power transitions. data retention - 5,000 program/erase cycles (with 4 bit / 528 byte ecc) - 10 years data retention package - H27U8G8T2Btr-bx : 48-pin tsop1 (12 x 20 x 1.2 mm) - H27U8G8T2Btr-bx (lead & halogen free) www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 4 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 1. summary description hynix nand H27U8G8T2B series have 1024 m x 8 bit with spare 32 m x 8 bit capacity. the devi ce is offered in 3.3 v vcc power supply, and with x8 i/o interface. its nand cell provid es the most cost-effective so lution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. the device contains 2048 blocks, composed by 128 pages. ever y cell holds two bits. a program operation allows to write the 4224 byte page in typical 800 us and an erase operation can be performed in typical 2.5 ms on a 512 k byte block. in addition to this, thanks to multi-plan e architecture, it is possible to program 2 pages a time (one per each plane) or to read 2 pages a time (one per each plane) to erase 2 bl ocks a time (again, one per each plane). as a consequence, multiplane architecture allows program time reduction and erase time reduction. data in the page can be read out at 25ns cycle time per by te. the i/o pins serve as the ports for address and data input/ output as well as command input. this interface allows a re duced pin count and easy migration towards different densities, without any rearrang ement of footprint. commands, data and addresses are sy nchronously introduced using ce, we , re , ale and cle input pin. the on-chip program/erase controller automates all read, program and eras e functions including pulse re petition, where required, and internal verification and margining of data. th e modify operations can be locked using the wp input. the output pin r/b (open drain buffer) signals the status of the device during each operation. in a system with multiple memories the r/b pins can be connected all together to provide a global status signal. the copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. data read out after copy back read (both for single and multiplane cases) is allowed. even the write-intensive systems can take advantage of th e H27U8G8T2B series extended reliability of 5 k program/ erase cycles by providing ecc (error correcting code) with real time mapping-out algorithm. the chip supports ce don't care function. this function allows the direct download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not stop the read operation. this device includes also extra features li ke otp/unique id area, read id2 extension. the H27U8G8T2B is available in 48-tsop1 12 x 20 mm. 1.1 product list part number organization vcc range package H27U8G8T2B x8 2.7v ~ 3.6v 48-tsop1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 5 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 9&& 966 :3 &/( $/( 5( :( &( ,2a,2 5% figure 2 : 48-tsop1 contact, x8 device io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection figure 1 : logic diagram table 1 : signal names 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 6 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 1.2 pin description table 2 : pin description note : 1. a 0.1uf capacitor should be connecte d between the vcc supply voltage pin an d the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. pin name description io0 ~ io7 data inputs/outputs the io pins allow to input command, address and da ta and to output data during read / program operations. the inputs are latched on th e rising edge of write enable (we ). the i/o buffer float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the address register on the rising edge of write enable (we ). ce chip enable this input controls the selection of the device. we write enable this input acts as clock to latch command, addre ss and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out co ntrol, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protec tion against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 7 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 3 : array organization table 3 : address cycle map note: 1. l must be set to low. 2. 1st & 2nd cycle are column address. 3. 3rd to 5th cycle are row address. io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 a12 l (1) l (1) l (1) 3rd cycle a13 a14 a15 a16 a17 a18 a19 a20 4th cycle a21 a22 a23 a24 a25 a26 a27 a28 5th cycle a29 a30 l (1) l (1) l (1) l (1) l (1) l (1) 0 plane 4k bytes 128 bytes i/o0 ~ 7 1 page = (4k+128) bytes 1 block = (4k+128) bytes x 128 pages = (512k+16k) bytes 1 device = (512k+16k)byte x 2048 block = 8 gbit page buffer 1024 blocks per plane 2048 blocks per device 1 3 2044 2045 2046 2047 2 0 1 plane . . . . . . www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 8 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 4 : command set note : with the ce don't care option ce high during latency time does not stop the read operation table 5 : mode selection function 1st 2nd 3rd 4th acceptable command during busy page read 00h 30h - - multi-plane read 60h 60h 30h - read for copy-back 00h 35h - - multiplane read for copyback 60h 60h 35h - read id 90h - - - reset ffh - - - yes page program 80h 10h - - copy back program 85h 10h - - multi-plane program 80h 11h 81h 10h multi-plane copy back program 85h 11h 81h 10h block erase 60h d0h - - multi-plane block erase 60h 60h d0h - read status register 70h - - - yes random data input 85h - - - random data output 05h e0h - - multi-plane random data output 00h 05h e0h - page program with backward compatibility (2 kb) 80h 11h 80h 10h copy back program with backward compatibility (2 kb) 85h 11h 85h 10h cle ale ce we re wp mode hllrisinghx read mode command input l h l rising h x address input (5 cycles) hllrisinghh write mode command input l h l rising h h address input (5 cycles) l l l rising h h data input l l l h falling x data output x x x h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0 v / vccstand by www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 9 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 2. bus operation there are six standard bus operations that control the device. these are comma nd input, address input, data input, data output, write protect, and standby. typically glitches less than 3 ns on ch ip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip en- able low, command latch enable high, address latch enable lo w and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify oper ation (write/erase) the write protect pin must be high. see figure 5 and table 12 for detail s of the timings requirements. 2.2 address input. address input bus operation allows the insertion of the memory address. to insert the 31 bits needed to access the 8 gbit device, 5 clock cycles are needed. addresses are accepted with chip enable low, address latch enable high, command latch enable low and read enable high and latched on the ri sing edge of write enable. moreover for commands that starts a modify operation (write/erase) the writ e protect pin must be high. see figure 6 and table 12 for details of the timings requirements. in addition, addresses over the addressable spac e are disregarded even if the user sets them during com- mand insertion. 2.3 data input. data input bus operation allows to feed to the device the data to be programmed. the data insertion is serially and timed by the write enable cycles. data are accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 7 and table 12 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the memory arra y and to check the status register content, the lock status and the id data. data can be serial ly shifted out toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figure 8, 9, 10 and tabl e 12 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation does not start and the content of the memory is not altered or it is interrupted without guarantee about memory co ntent not being altered. write protect pin is not latched by write enable, so as to ensure protection even during power up phases. 2.6 standby. in standby mode the device is deselect ed, outputs are disabled and power consum ption is reduced. stand-by is obtained holding high, at least for 10us, ce pin. www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 10 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 3. device operation 3.1 page read. upon initial power up, the device defaults to read mode. this operation is also initiated by writ ing 00h and 30h to the command register along with five address cycles. after a 1st pa ge read operation, device rema ins in read mode, that is to say that a 2nd page read can start just by inputting 5 addr ess cycles and read confirm command; in other words 00h com- mand cycle is not necessary. also after power up device is in read mode, so 00h command cycle is not necessary to start a read operation. any operation different from read or ra ndom data output causes the device to exit read mode. two types of read operations are available: random and serial read in a page. the random read mode is enabled when the page address is changed. the 4,224 bytes of data within th e selected page are transferred to the data registers in less than 60us (tr). the system contro ller may detect the completion of this data transfer (tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be re ad out in 25ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output th e data starting from the selected column address up to the last column address in the page. the device may output random data in a page instead of th e consecutive sequential data by writing random data output command (05h-e0h as in figure 13) the column address of next data, whic h is going to be output, may be chan ged to the address which follows random data output command. random data output can be operated regardless of how many times it is done in a page. check figure 11, figure 12 and figure 13 as a reference. 3.2 multiplane page read multi-plane page read is an extension of page read for a single plane. since the device is equipped with two memory planes, a read of two pages (one for each plane) is enabled by activating two se ts of 4,224 byte page registers(one for each plane). multi-plane page read is initiated by repeating command 60h follow ed by three address cycle twice and then by entering 30h confirm command. in this case only the same page of the same block can be selected from each plane. after read confirm command (30h) the 8,44 8 bytes of data within the selected two pages are transferred into the data registers in less than 60us(tr). the system controller can dete ct the completion of data tran sfer (tr) by monitoring the output of r/b pin. once the data are loaded into the data registers, the first plane's data must be read out by issuing command 00h with five address cycles (all 00h), command 05h with tw o column address and finall y e0h and then toggling re : if two column address is 00h, then the read-out starts from the beginning of the page, otherwise data-out will start from selected column for random data-out. the second plane's data must be read out using the comman d sequence command 00h with fi ve address cycles (all 00h except a20=1), command 05h with two column address and finally e0h and then toggling re : if two column address is 00h, then the read-out starts from the be ginning of the page, otherwise data-out wi ll start from selected column for random data out. to execute multiple random data-out within the same tw o pages selected, the command sequence is command 00h with five address cycles, command 05h with two column address and finally e0h: in 5 address cycles a20=0 allows random read in 1st plane page, while a20=1 allows random read in 2nd plane page (figure 14). restrictions and details for multi-plane page read are shown in figure 14. multi- plane read must be used in the block which has been programmed with multi-plane page program. www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 11 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 3.3 page program the device is programmed by page. only a single partial or complete page programming operation within the same page, without an intervening erase operation, is allowed the addressing must be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 4,224 data bytes may be loaded into the data register, followed by a non- volatile memory programming period where the loaded data are programmed into the appropriate cells. the serial data loading period begins by inputting the serial data input command (80h), followed by five address cycles input and then zero or more serial da ta input cycles. the words other than th ose to be programmed do not need to be loaded. the device supports random data input in a page. th e column address of next data , which will be entered, may be changed to the address which follows random data input command (85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the progra mming process. writing 10h al one without previously en- tering the serial data will not initiate the programming process. the internal wr ite state controller automatically executes the algorithms and timings nece ssary for program and verify, th ereby freeing the system cont roller for other tasks. once the program process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and reset command are accepted while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be tested to check for fails in the program operation. the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register re- mains in read status command mode until another valid comm and is written to the command register. figure 15 and fig- ure 17 detail the sequence. 3.4 multiplane page program device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane. a multiple plane program cycle consists of a double serial da ta loading period in which up to 8,448 bytes of data may be loaded into the data register, followed by a non-volatile memory programming period when the loaded data are pro- grammed into the appropriate cells. the serial data loadin g period begins by inputtin g the serial data input command (80h), followed by the five address cycles input and then zero or more serial data for the 1st page. address for this page must be within 1st plane (a<20>=0) and a<19:13> and a<30:21> must be fixed low. data of 1st page other than those to be programmed do not need to be loaded. the device suppo rts random data input exactly like a normal page program operation. the dummy page program conf irm command (11h) stops 1st page data input and the device goes busy for a short time (tdbsy). once it has returned ready, 81h command must be issued, fo llowed by page address cycles and zero or more serial data input cycles. address for this page must be within 2nd plane (a<20>=1) and a<19:13> and a<30:21> must be the valid addresses. the data of 2nd page other than those to be progra mmed do not need to be loaded. program confirm command (10h) makes parallel programming of both pages start. user can check operation status by r/b pin or read status register command, as if it were a normal page program; status register command is also available during dum- my busy time (tdbsy). in case of fail in 1st or 2nd page progra m, fail bit of status register will be set: the device supports pass/fail status of each plane (io0: total; io1: plane0; io2: plane1). figure 16 details the sequence. 3.5 block erase the block erase operation is done on a block basis. block addr ess loading is accomplished givi ng 3 address cycles initiated by an erase setup command (60h). only addresses a20 to a30 are valid while a13 to a19 are ignored. the erase confirm command (d0h) following the block address lo ading initiates the internal erasing proc ess. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condi- tions. at the rising edge of we after the erase confirm command input, the inte rnal write controller handles erase and erase- verify. once the erase process starts, the read status register comm and may be entered to read the status register. the system controller can detect the comple tion of an erase by monitoring the rb# outp ut, or the status bit (i/o 6) of the status register. only the read status command and reset command ar e valid while erasing is in progress. when the erase op- eration is completed, the write status bit (i/o 0) may be checked. figure 18 details the sequence. www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 12 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 3.6 multiplane block erase multiple plane erase allows parallel erase of two blocks, one per each plane. block erase setup command (60h) must be repeated two times, each time follow ed by 1st and 2nd block address cycles respectively (3 cycles each). as for block er ase, d0h command makes this operation start. multi-plane erase does not need an y dummy busy time between 1st and 2nd block address cycles insertion. address limitation required for multiple plane program applies al so to multiple plane erase, as well as operation progress can be checked like for multiple plane pr ogram. figure 19 details the sequence. 3.7 copy back program copy-back program with read for copy-back is configured to quickly and efficiently rewrite data stored in one page with- out data reloading when the bit error is not in data stored. since th e time-consuming re-loading cycles are removed, the system performance is improved. the benefit is especially obvi ous when a portion of block is updated and the rest of the block also needs to be copied to the ne wly assigned free block. copy -back operation is a sequenti al execution of read for copy-back and of copy-back program with the destination page address. a read operation with "35h" command and the address of the source page moves the whole 4,224-byte into th e internal data buffer. a bit error is checked by reading sequentially the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy- back program operation is initiated by issuing page-copy dat a-input command (85h) with dest ination page address. actual programming operation begins after program confirm comman d (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the rb# outp ut, or the status bit (i/o 6) of the status register. when the copy-back program is complete, the write status bit (i/o 0) may be checked (figure 20). the command reg- ister remains in read status command mode until another vali d command is written to the command register. during copy- back program, data modification is possible using ra ndom data input command (85h) as shown in figure 21. copy-back program operation is allowed only within the sa me memory plane. 3.8 multiplane copy back program two-plane copy-back program is an extens ion of copy-back program, for a single plane with 4,224 byte page registers. as for single plane copy-back, a multi plane read operation wi th "35h" (multi plane read fo r copy-back) command and the address of the source pages moves the whol e 4,224-byte of each page into the internal data buffer of each plane. since the device is equipped with two memory planes, activating th e two sets of 4,224 byte page registers enables a simultane- ous programming of two pages. figure 22 and figure 23 show the details of th e command sequence for the multi-plane copy-back operation in standard operation mode. in order to redu ce the buffer size required by host side (8kb buffer size) to perform this operation, new multiplane copy-back progra m flows have been introduced as shown from figure 24 to figure 25. as depictured the sequences of data out followed by data input for each plane can be performed an indefinite number of times, which depend on the buffer size used by host (e.g. figure 24 shows the sequence for a host equipped with a 4kb buffer size, whereas the figure 25 shows th e sequence for a host equipp ed with 2kb buffer size). 3.9 read status register the device contains a status register which may be read to find out whether a read, program or erase operation is com- pleted, and whether the program or erase operation is comp leted successfully. after writ ing 70h command to the command register, a read cycle outputs the cont ent of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 13 for specific status register defi nitions and to figure 10 for status read se quence. the command regi ster remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting new read cycles. www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 13 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 3.10 read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad- dress input of 00h. five read cycles sequ entially output the manufacturer code (2 0h), and the device code and 3rd, 4th and 5th cycle id, respectively. the command register remains in read id mode un til further commands are issued to it. figure 26 shows the operation sequence, wh ile following table 15, table 16, table 17, and table 18 explain the byte mean- ing. complete read id code table is table 14. 3.11 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operatio n will abort these operations. the contents of memory cells being altered are no longer valid, as th e data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp is high. refer to table 13 for device status after reset operation. if the device is already in re set state a new reset command will not be accepted by the com- mand register. the r/b pin transitions to low for trst after the reset command is written (see figure 27). www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 14 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 4. other features 4.1 data protection the device is designed to offer protecti on from any involuntary program/erase during power-transitions. an internal volt- age detector disables all functions wh enever vcc is below about 2.0 v. wp pin provides hardware protection and is recom- mended to be kept at v il during power-up and power-down. a recovery time is required before internal circuit gets ready for any command sequences as shown in figure 28. the two-step command sequen ce for program/erase provides addi- tional software protection. 4.2 ready/busy the device has a ready/busy output that provides method of indicating the comple tion of a page program, erase, copy- back, cache program and random read completion. the r/b pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it returns to high when the internal controll er has finished the operation. the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy (i bu sy), an appropriate value can be ob tained with the following reference chart (figure 29). its value can be determined by the following guidance. 4.3 system interface using ce don't care to simplify system interface, ce may be deasserted during data loading or sequential data reading as shown figure 30 and 31. so, it is possible to connect nand flash to a microp rocessor. the only function th at was removed from standard nand flash to make ce don't care operation was disabling of the automatic sequenti al read function. www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 15 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 6 : number of valid blocks note: 1. the 1st block is guaranteed to be a valid block at the time of shipment. table 7 : absulute maximum ratings note: 1. block 0 is guaranteed to be valid at the time of the ship ment up to 1k p/e cycles. the number of valid blocks is based on single plane operations and may be little lower on two plane operations. 2. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these ar e stress ratings only and operation of the device at these or any other conditions above those indica ted in the operating sections of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. refer also to the hynix sure program and other relevant quality documents. 3. minimum voltage may undershoot to -2 v during tr ansition and for less than 20ns during transitions. parameter symbol min typ max unit valid block number n vb 1998 2048 blocks symbol parameter value unit t a ambient operating temperature (temperature range option 1) 0 to 70 c ambient operating temperature (temperature range option 6) ? 40 to 85 c t bias temperature under bias ? 50 to 125 c t stg storage temperature ? 65 to 150 c v io (2) input or output voltage ? 0.6 to 4.6 v v cc supply voltage ? 0.6 to 4.6 v www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 16 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 4 : block diagram address register/ counter program erase controller hv generation command interface logic command register data register io re buffers y decoder page buffer x d e c o d e r 8192 mbit + 256 mbit nand flash memory array wp ce we cle ale a30 ~ a0 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 17 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 8 : dc and opea ting characteristics table 9 : ac test conditions parameter symbol test conditions 3.3 volt unit min typ max operating current sequential read i cc1 t rc = 25 ns, ce = v il, i out = 0 ma - 15 30 ma program i cc2 - - 15 30 ma erase i cc3 - - 15 30 ma stand-by current (ttl) i cc4 ce = v ih , wp = 0 v/v cc --1ma stand-by current (cmos) i cc5 ce = v cc - 0.2, wp = 0 v / www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 18 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 10 : pin capacitance (ta = 25 , www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 19 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 12 : ac timing characteristics note : 1) if reset command (ffh) is written at ready st ate, the device goes into busy for maximum 5 us 2) program / erase enable operation : wp high to we high program / erase disable operation : wp low to we high parameter symbol 3.3 volt unit min max cle setup time t cls 12 ns cle hold time t clh 5ns ce setup time t cs 20 ns ce hold time t ch 5ns we pulse width t wp 12 ns ale setup time t als 12 ns ale hold time t alh 5ns data setup time t ds 12 ns data hold time t dh 5ns write cycle time t wc 25 ns we high hold time t wh 10 ns address to data loading time t adl 70 ns data transfer from cell to register t r 60 us ale to re delay t ar 10 ns cle to re delay t clr 10 ns ready to re low t rr 20 ns re pulse width t rp 12 ns we high to busy t wb 100 ns read cycle time t rc 25 ns re access time t rea 20 ns re high to output hi-z t rhz 100 ns ce access time t cea 30 ns ce high to output hi-z t chz 50 ns re high to output hold t rhoh 15 ns re low to output hold t rloh 5ns ce low to we low t cr 10 ns ce high to output hold t coh 15 ns re high hold time t reh 10 ns output hi-z to re low t ir 0ns re high to we low t rhw 100 ns we high to re low t whr 80 ns device resetting time (read/program/erase) t rst 2/20/500 1) us write protection time t ww 2) 100 ns www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 20 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 13 : status register coding table 14 : device identifier coding table 15 : read id data table io page program block erase read coding 0 pass / fail pass / fail na pass: ?0? fail: ?1? 1 plane 0 pass / fail plane 0 pass / fail na pass: ?0? fail : ?1? 2 plane 1 pass / fail plane 1 pass / fail na pass: ?0? fail : ?1? 3na na na - 4na na na - 5 ready/busy ready/busy ready/busy busy: ?0? ready:?1? 6 ready/busy ready/busy ready/busy busy: ?0? ready:?1? 7 write protect write protect write protect protected: ?0? not protected: ?1? device identifier byte description 1 st manufacturer code 2 nd device identifier 3 rd internal chip number, cell type, etc. 4 th page size, block size, spare size, organization 5 th multiplane information part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) 3rd cycle 4th cycle 5th cycle H27U8G8T2B 3.3v x8 adh d3h 14h b6h 34h www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 21 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 16 : 3rd byte of device identifier description table 17 : 4th byte of device identifier description description io7 io6 io5 io4 io3 io2 io1 io0 die / package 1 2 4 8 0 0 0 1 1 0 1 1 cell type 1 bit / cell 2 bit / cell 3 bit / cell 4 bit / cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between different dice not supported supported 0 1 write cache not supported supported 0 1 description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time 50 ns 30 ns 25 ns reserved 0 0 1 1 0 1 0 1 block size (without spare area) 64k 128k 256k 512kb 0 0 0 1 1 0 1 1 organization x8 x16 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 22 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash table 18 : 5th byte of device identifier description description dq7 dq6-5-4 dq3-2 dq1-0 planes 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare) 512mb 1gb 2gb 4gb 8gb reserved reserved reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 00 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 23 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 5 : command latch cycle figure 6 : address latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ w&/6 w&6 w:& w$/6 w$/6 w$/6 w$/6 w$/6 w$/+ w$/+ w$/+ w$/+ w$/+ w:& w:& w:& w:3 w:3 w:+ w:3 w:3 w:+ w:+ w:+ w'6 &ro$gg &/( &( :( $/( ,2[ &ro$gg 5rz$gg 5rz$gg 5rz$gg w'6 w'6 w'6 w'6 w'+ w'+ w'+ w'+ w'+ www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 24 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 7 : input data latch cycle figure 8 : sequential out cycle after read (cle = l, we = h, ale = l) twc tclh tch twp twh din 1 din 0 din final twh tdh tdh tdh tds tds tds twp twp cle ale ce i/ox we tals trc ce re i/ox r/b trea trr dout dout dout notes: transition is measured at +/-200mv from steady state voltage with load. this parameter is sampled and not 100% tested. (tchz, trhz) trhoh starts to be valid when frequency is lower than 33mhz. trloh is valid when frequency is higher than 33mhz trea trhz trhz trea tchz tcoh trhoh treh www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 25 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 9 : sequential out cycle after read (edo type cle = l, we = h, ale = l) figure 10 : read status register w5& w53 w5(+ w5($ w&5 w5/2+ w55 w5($ w&+= w&2+ w5+= w5+2+ 'rxw 'rxw &( 5( ,2[ 5% 1rwhv7udqvlwlrqlvphdvxuhgdwp9iurpvwhdg\vwdwhyr owdjhzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw&+= w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhuwkdq 0+] w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &5 w '6 w 5($ w &+= w &2+ w 5+= w 5+2+ k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 26 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 11 : page read operation figure 12 : page read operation (intercepted by ce ) cle ale ce i/ox we re r/d t wc t clr t rr 00h 30h col.add1 column address row address col.add2 row add1 row add2 row add3 busy dout n dout n+ dout m t wb t ar t r t rc t rhz g twb tar tchz tcoh trc tr trr busy 00h 30h dout n dout n+1 dout n+2 col. add1 col. add2 row add1 row add2 row add3 column address row address cle ce we ale re i/ox r/b www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 27 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 13 : random data output &/( $/( &( 5( 5% ,2[ :( w&/5 k &roxpq$gguhvv 5rz$gguhvv %xv\ k k (k 'rxw1 'rxw0 'rxw1 'rxw0 &ro$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg &roxpq$gguhvv &ro$gg &ro$gg w5 w5& w:% w$5 w55 w:+5 w5($ w5+: www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 28 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 14 : multiplane read operation with random data output twc twc twc twc tclr twhr trhw trea trc twhr trea trc tclr twb tr busy 1 1 60h 60h cle ale ce re r/b i/ox we a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a0 ~ a12 : valid a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid 00h 05h e0h 30h row. add1 row. add2 row. add3 row. add1 col. add1 co2. add1 col. add1 dout n dout n+1 dout m dout m+1 co2. add1 row. add2 row. add3 row address row. add1 row. add2 row. add3 row address column address 00h row. add1 col. add1 co2. add1 row. add2 row. add3 row address column address column address 05h e0h col. add1 co2. add1 column address row address cle ale ce re r/b i/ox we www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 29 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 15 : page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro $gg 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 127(6w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodggu hvvf\fohwrwkh:(ulvlqjhgjhriiluvwgdwdf\foh 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2 6xffhvvixo3urjudp ,2 (uurulq3urjudp xswrp%\wh 6huldo,qsxw &ro $gg 5rz $gg 5rz $gg 5rz $gg 'lq 1 'lq 0 k k ,2 w:& w:% w352* w:+5 w:& w$'/ www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 30 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 16 : multiplane page program multi-plane page program operation ale cle ce re r/b i/ox we r/b i/o0~7 ex.) two-plane page program twc 81h 70h i/o col add 1,2 & row add 1,2 3 4224 byte data col add 1,2 & row add 1,2 3 4224 byte data note a0 ~ a12 valid a13 ~ a19 fixed low a20 fixed low a21 ~ a30 fixed low a0 ~ a12 valid a13 ~ a19 valid a20 fixed high a21 ~ a30 valid note: any command between 11h and 81h is prohibted except 70h and ff tdbsy tprog serial data input command column address page row address 1 up to 4224 byte data serial input program command (dummy) 80h 11h 81h 10h 70h address & data input address & data input 11h din n din m serial input program command (true) 10h din n din m col.add1 80h col.add2 row add1 row add2 row add3 row add3 col.add1 col.add2 row add1 row add2 twb twhr tprog twb tdbsy tdbsy : 1us (typ.) 2us (max.) i/o 1 = 0 successful program in plane 0 i/o 1 = 1 error in plane 0 i/o 2 = 0 successful program in plane 1 i/o 2 = 1 error in plane1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 31 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 17 : random data input &/( $ /( &( 5( 5% ,2[ :( w:& k 'lq 1 'lq 0 'lq - 'lq . k k k ,2 &ro$gg &ro$gg &ro$gg &ro$gg 5zr$gg 5zr$gg 5zr$gg w:& w:% w:+5 w352* 6huldo'dwd ,qsxw&rppdqg 5dqgrp'dwd ,qsxw&rppdqg &roxpq$gguhvv &roxpq$gguhvv 5rz$gguhvv 127(6w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodg guhvvf\fohwrwkh:(uvlqjhgjhriiluvwgdwdf\foh 6huldo,qsxw 6huldo,qsxw 3urjudp &rppdqg 5hdg6wdwxv &rppdqg w:& w$'/ w$'/ www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 32 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 18 : block erase w:& &/( &( :( $/( 5( ,2 [ 5% w:% w%(56 %86< k ,2 5rz$gg 5rz$gg 5rz$gg k $xwr%orfn(udvh6hwxs&rppdqg (udvh&rqilup&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh %orfn$gguhvv 'k www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 33 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 19 : multiplane block erase row address block erase setup command1 block erase setup command2 erase confirm command read status command busy row address ex.) address restriction for multi-plane block erase operation ale cle ce re r/b i/ox we r/b i/o0~7 twc 60h 60h row add1,2,3 row add1,2,3 a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : valid address address 60h 70h d0h 60h d0h 70h i/o row add1 row add1 row add2 row add2 row add3 row add3 twc twb tbers tbers twhr i/o 1 = 0 successful program in plane 0 i/o 1 = 1 error in plane 0 i/o 2 = 0 successful program in plane 1 i/o 2 = 1 error in plane1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 34 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 20 : copy back program operation twc twb tr col add 1,2 & row add 1,2,3 col add 1,2 & row add 1,2,3 data in 10h 70h i/ox address 85h 00h 00h e ad command column address column address page row address error correction data input copyback program command page row address read confirm command 35h 85h data n data m 10h 70h i/o col add1 col add2 row add1 row add2 row add3 row add1 row add2 row add3 col add1 col add2 35h address tprog tr trrog - 0 error correction data input data n data m data out www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 35 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 21 : copy back with random data input &/( &( :( w:& w:% w5 w5& w$'/ w352* w:+5 w:% $ /( 5( k k k ,2 k k 'dwd 'dwd 'dwd 'dwd k 'dwd 'dwd %xv\ 127(6w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodgg uhvvf\fohwrwkh:(ulvlqjhgjhriiluvwgdwdf\foh &roxpq$gguhvv &roxpq$gguhvv 'dwd2xw 'dwd,q 5rz$gguhvv 5rz$gguhvv 5hdo6wdwxv&rppdqg %xv\ ,2 6xfhvvixo3urjudp ,2 (uurulq3urjudp &rs\%dfn'dwd ,qsxw&rppdqg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &roxpq$gguhvv &ro $gg &ro $gg ,2[ 5% 5% w5 w352* ,2a k k &rodgg 5rzdgg &rodgg 5rzdgg &rodgg k k k ,2[ k dgguhvv dgguhvv dgguhvv 'dwdrxw 'dwd,q 'dwd,q www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 36 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 22 : multiplane copy back 60h row add. 1,2,3 a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid row add. 1,2,3 tr 1 60h 35h address (3 cycle) address (3 cycle) 00h r/b i/ox 05h e0h data output address (5 cycle) address (2 cycle) col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : fixed low a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid a0 ~ a12 : valid 00h 85h 11h add. (5cycles) 81h 10h 70h add. (5cycles) 05h e0h data output address (5 cycle) address (2 cycle) tdbsy tprog 1 2 3 2 3 r/b i/ox r/b i/ox r/b i/ox i/o 1 = 0 successful program in plane 0 i/o 1 = 1 error in plane 0 i/o 2 = 0 successful program in plane 1 i/o 2 = 1 error in plane1 i/o www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 37 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 23 : multiplane copy back with random data input 60h row add. 1,2,3 a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid row add. 1,2,3 tr 1 60h 35h address (3 cycle) address (3 cycle) 00h r/b i/ox 05h e0h data output address (5 cycle) address (5 cycles) address (2 cycle) col. add 1,2 & row add. 1,2,3 col. add 1,2 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : valid 00h 85h 05h e0h data output address (5 cycle) address (2 cycle) tdbsy tprog 1 2 3 2 3 4 4 r/b i/ox r/b i/ox 85h 11h data data address (2 cycles) address (5 cycles) col. add 1,2 81h 85h 10h data data address (2 cycles) i/ox i/ox r/b r/b note 1. copy back program operation is allowed only within the same memory plane. 2. an y command between 11h and 81h is p rohibited exce p t 70h and ffh www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 38 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 24 : multiplane copy back for 4 kb buffer 60h row add. 1,2,3 a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid row add. 1,2,3 tr 1 60h 35h address (3 cycle) address (3 cycle) 00h r/b i/ox 05h e0h data output (4kb) address (5 cycle) address (5 cycles) address (2 cycle) col. add 1,2 & row add. 1,2,3 col. add 1,2 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : valid 00h 85h 05h e0h data output (4kb) address (5 cycle) address (2 cycle) tdbsy tprog 1 2 4 3 2 4 3 r/b i/ox r/b i/ox 85h 11h data data address (2 cycles) address (5 cycles) col. add 1,2 81h 85h 10h data data address (2 cycles) i/ox i/ox r/b r/b note 1. copy back program operation is allowed only within the same memory plane. 2. any command between 11h and 81h is prohibited except 70h and ffh w???gi????? k???gv????? w????gw z?????gh?????? w????gx z?????gh?????? w????gw z?????gh?????? w????gx z?????gh?????? 1 1 6 6 2 4 5 3 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 39 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 25 : multi-plane co py back for 2 kb buffer (1) 60h row add. 1,2,3 a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid row add. 1,2,3 tr 1 60h 35h address (3 cycle) address (3 cycle) 00h r/b i/ox 05h e0h data output ( 2 kb ) address (5 cycle) address (5 cycles) address (2 cycle) col. add 1,2 & row add. 1,2,3 col. add 1,2 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 destination address a0 ~ a12 : valid 00h 85h 05h e0h data output ( 2 kb ) address (5 cycle) address (2 cycle) tdbsy 1 2 6 5 4 5 r/b i/ox r/b i/ox 85h 11h data data address (2 cycles) i/ox r/b col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low a0 ~ a12 : valid 00h 05h e0h data output ( 2 kb ) address (5 cycle) address (2 cycle) 3 4 r/b i/ox a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : fixed low a21 ~ a30 : fixed low address (5 cycles) col. add 1,2 col. add 1,2 & row add. 1,2,3 destination address 85h 2 3 85h data data address (2 cycles) i/ox r/b www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 40 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 25 : multi-plane co py back for 2 kb buffer (2) a0 ~ a12 : valid a13 ~ a19 : valid a20 : fixed high a21 ~ a30 : valid col. add 1,2 & row add. 1,2,3 destination address tprog 8 address (5 cycles) col. add 1,2 81h 85h 10h data data address (2 cycles) i/ox r/b col. add 1,2 & row add. 1,2,3 col. add 1,2 a0 ~ a12 : fixed low a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low a0 ~ a12 : valid 00h 05h e0h data output ( 2 kb) address (5 cycle) address (2 cycle) 7 8 r/b i/ox a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : fixed high a21 ~ a30 : fixed low address (5 cycles) col. add 1,2 col. add 1,2 & row add. 1,2,3 destination address 85h 6 7 85h data data address (2 cycles) i/ox r/b note 1. copy back program operation is allowed only within the same memory plane. 2. any command between 11h and 81h is prohibited except 70h and ffh w???gi????? k???gv????? w????gw z?????gh?????? w????gx z?????gh?????? w????gw z?????gh?????? w????gx z?????gh?????? 1 1 10 10 4 2 8 6 7 9 3 5 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 41 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 26 : read id figure 27 : reset operation 90h cle ce we ale re i/o x 00h trea read id command address 1 cycle maker code device code adh 4th cycle 5th cycle 3rd cycle d3h b6h 34h 14h tar ))k w 567 :( $/( &/( 5( ,2 5% www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 42 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 28 : power on and data protection timing vcc 2.5v 2.7v 2.5v 2.7v 100us max invalid 0v ce v il v operation 1ms max ih v il wp readybusy dont care dont care dont care www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 43 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 29 : ready / busy pin electrical specifications rp value guidence rp (min) = = where il is the sum of the input currnts of all devices tied to the r/b pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 3.3 v, ta = 25 c, c l = 50 pf fig. rp vs tr, tf & rp vs ibusy vcc (max.) - v ol (max.) 3.2v p$?, l i ol + ?, l rp ibusy rp (ohm) ibusy ibusy [a] tr, tf [s] tf 3.3 381 290 1.65 96 189 1.1 0.825 4.2 4.2 4.2 4.2 busy ready vcc v oh tr tf v ol v ol : 0.4v, v oh : 2.4v vcc 300n 3m 1k 2k 3k 4k 200n 2m 100n 1m gnd device open drain output r/b www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 44 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 30 : program operation with ce don?t care figure 31 : read operation with ce don?t care &(grq?wfduh k 6wduw$gg&\foh 'dwd,qsxw k 'dwd,qsxw &/( &( :( $/( ,2[ ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 45 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affe ct the performance of valid blocks becaus e it is isolated from the bit line and common source line by a select transistor. the devices are su pplied with all the locations in side valid blocks erase (ffh). the bad block information is written prior to shipping. any bloc k where the 1st byte in the spare area of the last or (last- 2)th page (if the last page is bad) does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be er ased. for the system to be able to recognize the bad blocks based on the original information it is recommended to crea te a bad block table following the flowchart shown in figure 32. the 1st block, which is placed on 00h address, is guaranteed to be a valid one. figure 32 : bad block management flowchart note : - make sure that ffh at the column address 4,096 of the last page and last-2th page <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 46 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash bad block replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these addition al bad blocks can be identified as atte mpts to program or erase them will give errors in the status register. the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replac ed block to an available valid block. refer to table 19 and figure 33 for the recommended procedur e to follow if an error occurs during an operation . table 19 : block failure figure 33 : bad block replacement note : 1. an error occurs on the block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. n th data of block a which is in controll er buffer memory is copied into n th page of block b 4. bad block table should be updated to prevent from erasing or programming block a operation recommended procedure erase block replacement program block replacement read ecc (with 4 bits / 512 bytes) data buffer memor y of the controller block a block b n page ffh (2) (3) data ffh failure (1) th www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 47 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 34~37) figure 35 : disable programming figure 34 : enable programming k k w :: :: w k k :( ,2[ :3 5% k w :: 'k figure 36 : enable erasing figure 37 : disable erasing k w 'k :: :( ,2[ :3 5% www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 48 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash the backward compatibilit y (2kbyte/page operation) 1. page program note : any command between 11h and 80h is prohibited except 70h and ffh. 2. copy back program note: 1. copy-back program operation is allowed only within the same memory plane. 2. any command between 11h and 85h is prohibited except 70h/f1h and ffh. 3. on the same plane, it?s prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page (source page) to an odd page(t arget page). therefore, the copy-back program is permitted just betw een odd address pages or even address pages 80h 11h 10h 80h 70h address & data input address & data input i/o0~7 r/b tdbsy tprog note a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : valid a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : valid a20 : must be same with the previous a21 ~ a30 : valid col. add 1,2 & row add. 1,2,3 up to 2112 byte data col. add 1,2 & row add. 1,2,3 up to 2112 byte data 00h 85h 85h 11h 10h data data 35h 1 data output add. (5cycles) add. (5cycles) add. (5cycles) a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : must be same with the source plane a21 ~ a30 : fixed low a0 ~ a12 : valid a13 ~ a19 : valid a20 : must be same with the source plane a21 ~ a30 : valid col. add 1,2 & row add. 1,2,3 source address col. add 1,2 & row add. 1,2,3 col. add 1,2 & row add. 1,2,3 up to 2112 byte data up to 2112 byte data destination address destination address 1 i/ox r/b i/ox r/b tdbsy tr tprog www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 49 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash 3. copy back program with random data input note: 1. copy-back program operation is allowed only within the same memory plane. 2. any command between 11h and 85h is prohibited except 70h/f1h and ffh. 3. on the same plane, it?s prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page (source page) to an odd page(t arget page). therefore, the copy-back program is permitted just betw een odd address pages or even address pages tr tdbsy tprog 1 1 2 2 00h 85h 85h 11h data data 35h data output add. (5cycles) add. (5cycles) add. (2cycles) col. add 1,2 & row add. 1,2,3 source address a0 ~ a12 : valid a13 ~ a19 : fixed low a20 : must be same with the source plane a21 ~ a30 : fixed low col. add 1,2 & row add. 1,2,3 col. add 1,2 destination address up to 2112 byte data up to 2112 byte data 85h 85h 10h data data add. (5cycles) add. (2cycles) col. add 1,2 i/ox r/b i/ox r/b i/ox r/b a0 ~ a12 : valid a13 ~ a19 : valid a20 : must be same with the soruce plane a21 ~ a30 : valid col. add 1,2 & row add. 1,2,3 destination address www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 50 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash paired page address information note: when program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged. table 20 : paired page address information paired page address paired page address group a group b group a group b ooh 04h 01h 05h 02h 08h 03h 09h 06h 0ch 07h 0dh 0ah 10h 0bh 11h 0eh 14h 0fh 15h 12h 18h 13h 19h 16h 1ch 17h 1dh 1ah 20h 1bh 21h 1eh 24h 1fh 25h 22h 28h 23h 29h 26h 2ch 27h 2dh 2ah 30h 2bh 31h 2eh 34h 2fh 35h 32h 38h 33h 39h 36h 3ch 37h 3dh 3ah 40h 3bh 41h 3eh 44h 3fh 45h 42h 48h 43h 49h 46h 4ch 47h 4dh 4ah 50h 4bh 51h 4eh 54h 4fh 55h 52h 58h 53h 59h 56h 5ch 57h 5dh 5ah 60h 5bh 61h 5eh 64h 5fh 65h 62h 68h 63h 69h 66h 6ch 67h 6dh 6ah 70h 6bh 71h 6eh 74h 6fh 75h 72h 78h 73h 79h 76h 7ch 77h 7dh 7ah 7eh 7bh 7fh www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 51 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash figure 38 : 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline t a b l e 2 1 : 4 8 - t s o p 1 - 4 8 - l e a d p l a s t i c t h i n s m a l l o u t l i n e , 1 2 x 2 0 m m , package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 ' $ ',( $ h % / . ( ( & &3 $ www.datasheet.co.kr datasheet pdf - http://www..net/
rev 0.0 / jul. 2008 52 1 preliminary H27U8G8T2B series 8 gbit (1024 m x 8 bit) nand flash marking information - tsop1 marking example k o r h 2 7 u 8 g 8 t 2 b y w w x x - hynix - kor - H27U8G8T2Bxx-xx h: hynix 27: nand flash u: power supply 8g: density 8 : bit organization t: classification 2: mode b: version x: package type x: package material x: bad block x: operating temperature - y: year (ex: 8=year 2008, 9= year 2009) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u (2.7 v~3.6 v) : 8 gbit : 8(x8) : m ulti level cell+ single die+large block : 2(1nce & 1r/nb; sequential row read disable) : 3rd generation : t(48-tsop1) : blank(normal), r(lead & halogen free) : b(included bad block), s(1~5 bad block), p(all good block) : c(0 x x - x x www.datasheet.co.kr datasheet pdf - http://www..net/

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